The Svalinn Framework Provides Comprehensive Analysis of Multibit Error Protection Overheads to Facilitate Better Architecture-level Design Choices

......As circuit feature sizes shrink, their capacitance and operating voltage become smaller, making it easier for a particle strike to influence circuit behavior. Technologies such as silicon on insulator (SOI) and FinFET significantly counteract this effect by decreasing the sensitive area in the transistor. However, the resulting single-event upset (SEU) rate is still nontrivial for common low-power designs or those that use dynamic voltage and frequency scaling (DVFS), especially in the context of increasing process variation. Most importantly, as a result of shrinking device sizes, the particle ‘‘blast area’’ covers a larger part of a circuit, potentially causing a single event, multiple upset (SEMU) within the same or across neighboring cells or logic components. These upsets can adversely affect dynamic and static charge in combinational and sequential circuits, respectively. Static RAM (SRAM) circuits (such as those in the register file, cache, and translation look-aside buffer) and sequential logic (latches and flip-flops) have always been considered vulnerable to soft errors and therefore protected in high-reliability products. However, combinational logic and data paths have been regarded as resilient for most purposes (except for those in safety-critical systems) due to sufficient error mitigation via different types of masking. In electrical masking, signals are constantly driven by their inputs; in logical masking, if a circuit is not sensitized to a signal, an error will not propagate; and in temporal masking, if an error does not appear at an output at the clock edge, it is not latched. However, as feature sizes decrease and masking becomes less effective, errors in combinational logic increase their contribution to the overall soft error rate (SER) and therefore become a concern even for commodity processors today. With the higher risk of multibit upsets and the increased vulnerability of combinational logic, more sophisticated soft error [3B2-9] mmi2013040010.3d 11/7/013 17:9 Page 2